commit 6b0757d6d46526f6cc0dcc525eea6e7760b5ee80
parent 9e9f4bd8c9da83de4219d93d0260d14c155d1b77
Author: AndrewLockVI <andrewlaack1@gmail.com>
Date: Sun, 21 Apr 2024 20:11:42 -0500
1:19 into lecture
Diffstat:
25 files changed, 253 insertions(+), 7 deletions(-)
diff --git a/BCD.md b/BCD.md
@@ -0,0 +1,17 @@
+# Binary Coded Decimal (BCD)
+
+CA L3
+
+## Notes
+
+**Definition:** Binary coded decimal (BCD) is the process of encoding a decimal where each digit is a fixed number of bits.
+
+Ex.
+
+Before: 10:37:49
+
+After: 0001 0000 : 0011 0111 : 0100 1001
+
+As you can see above, each digit is encode in a nibble.
+
+
diff --git a/BitSteering.md b/BitSteering.md
@@ -0,0 +1,11 @@
+# Bit Steering
+
+CA L3
+
+## Notes
+
+**Definition:** This is a bit in an instruction that determines how later bits are interpreted.
+
+A good example of this is an [[Opcode.md]]
+
+There are also other examples including Alpha's ([[ISA.md]]) ADD instruction which allows for permutations of the ADD instruction based on a bit passed to it as part of the instruction.
diff --git a/Blender.md b/Blender.md
@@ -5,7 +5,7 @@ CS331 W12 L3
## Notes
-The default file format is FBX (Filmbox) which can be imported into [[Unity]].
+The default file format is FBX (Filmbox) which can be imported into [[Unity.md]].
## Links
diff --git a/EigenVector.md b/CISC.md
diff --git a/CS331.md b/CS331.md
@@ -5,5 +5,6 @@ This is the index for my CS 332 notes.
## Main Links
-[[Unity]]
-[[Blender]]
+[[Unity.md]]
+[[Blender.md]]
+[[MathConceptsCS331.md]]
diff --git a/ComputerArchitecture.md b/ComputerArchitecture.md
@@ -21,18 +21,30 @@ Links to information learned from computer architecture course
[[SuperScalar.md]]
[[MooresLaw.md]]
[[ForwardThoughts.md]]
+[[DesignPoint.md]]
[[DRAMRowHammer.md]]
[[VonNeumannModel.md]]
[[BarrierSynchronization.md]]
[[MicroArchitecture.md]]
+[[Instruction.md]]
+[[Opcode.md]]
+[[BitSteering.md]]
+[[BCD.md]]
+[[ProgrammerVisibleState.md]]
+[[MUX.md]]
To do:
+[[ControlSignals.md]]
[[Hamming.md]]
[[PipelineControl.md]]
[[CircuitTechnology.md]]
+[[VLIW.md]]
[[SRAM.md]]
[[Adder.md]]
[[Cache.md]]
+[[RISC.md]]
+[[CISC.md]]
[[BloomFilter.md]]
[[CriticalPath.md]]
+[[MIPS.md]]
diff --git a/DesignPoint.md b/DesignPoint.md
@@ -0,0 +1,17 @@
+:computer-architecture:
+# Design Point
+
+CA L3
+
+## Notes
+
+**Definition:** The point of a computer's design including constraints of the system.
+
+Here are some of the design constraints:
+
+1. Cost
+2. Energy Consumption
+3. Performance
+4. Availability (how long can it run)
+5. Reliability and Correctness
+6. Time to Market
diff --git a/Determinant.md b/Determinant.md
@@ -0,0 +1,11 @@
+:cs331: :math: :linear-algebra:
+# Determinanat
+
+CS331 - Linear Algebra
+
+## Notes
+
+**Definition:** The determinant is the scaling factor of some area (or volume in 3d space) from before to after a linear transformation.
+
+
+This value can be negative if the space has been flipped. In 3d space, this means the volume after the tranformation is in left hand space if it was before in right hand space.
diff --git a/DotProduct.md b/DotProduct.md
@@ -0,0 +1,12 @@
+:cs331: :linear-algebra:
+# Dot Product
+
+CS331 + Linear Algebra
+
+## Notes
+
+**Definition:** The dot product of two vectors is the sum of their corresponding components.
+
+This can be visualized as the length of one vector, v, projected onto another vector, y, multiplied by the length of the vector y. Additionally, if two vectors generally have a different direction, their dot product is negative. This is why the on same side of plane algorithm works (see cs331 code), because if two vectors are on the same side of the normal vector of a plane, then they will both have negative or positive dot products.
+
+This value is zero if the vectors are orthogonal.
diff --git a/EigenVector.md b/EigenVector.md
@@ -1 +1,10 @@
-:todo:
+:ml: :cs331:
+# Eigen Vector
+
+Self Study
+
+## Notes
+
+**Definition:** An Eigen Vector is a non-zero vector that when a linear transformation is performed upon it, the resulting vector is only moved by a scalar multiple (remains on the same line).
+
+Associated with this, we also have an Eigen value which is the amount that a point on the Eigen Vector is distorted by (multiplied by this scalar)
diff --git a/ISA.md b/ISA.md
@@ -1,7 +1,7 @@
:computer-architecture:
# Instruction Set Architecture
-Computer Architecture L2
+Computer Architecture L(2,3)
## Notes
@@ -9,3 +9,45 @@ Computer Architecture L2
This is the agreed upon interface between os/vm/higher level things and lower level [[MicroArchitecture.md]]. This information is necessary to know for the OS developer.
+The ISA also includes register things and sometimes the CPU frequency/voltage.
+
+[[Pipelining.md]] is generally not part of the ISA on newer systems.
+
+Some ISAs have additional room for un-implemented instructions that would allow for future expansion.
+
+---
+
+0-address machines (stack machines) are machines that only take [[Opcode.md]] but not [[Operands.md]]. 0-address takes up less space in code, everything is already on the stack, but it can be very slow and can't express all computations easily (consider order of operations).
+
+2-address machines are source + destination for operands. This does not preserve the value of the destination which requires copying overhead. x86 is 2-address.
+
+3-address machines are source 1, source 2, and destination. Alpha is 3-address as is MIPS and ARM.
+
+---
+
+The ISA also defines the supported datatypes. Some common ones include int, float, character. Sometimes they can include linked lists, stacks, queues, and strings.
+
+With more/high level datatypes in the ISA we have smaller code, more cpu complexity, but simpler compilers. This basically means harder for [[MicroArchitecture.md]] development, but easier for compiler developer.
+
+This ties into semantic gap which describes the difference between the ISA and what programmers are trying to do with respect to datatypes and opcodes. When there are more datatypes, the semantic gap is low. The inverse is also true.
+
+Virtual memory support is also part of the ISA.
+
+
+---
+
+There is also another division in ISAs being load/store vs memory/memory architecture.
+
+Load/store allows instructions to only run on registers. These are most RISC ISAs including MIPS and ARM.
+
+Memory/memory can operate on memory locations as well as registers. These are most CISC ISAs including x86.
+
+---
+
+Orthogonal ISA
+
+Orthogonal ISAs allow for all opcodes to be used regardless of addressing mode.
+
+---
+
+
diff --git a/Instruction.md b/Instruction.md
@@ -0,0 +1,22 @@
+:computer-architecture: :isa:
+# Instruction
+
+CA L3
+
+## Notes
+
+**Definition:** An instruction is the most basic element of the hardware software interface which describes what to do and to who.
+
+An instruction is made of two parts, the [[Opcode.md]] describes what to do, and the [[Operands.md]] describe to who.
+
+There are also classes of instructions. These are the following 3:
+
+1. Operate Instructions
+ - This includes math
+2. Data Movement Instructions
+ - Moves data between IO devices (memory/storage)
+3. Control Flow Instructions
+ - Change sequence of instructions to execute
+
+
+See [[ISA.md]] for more about instruction sets.
diff --git a/MIPS.md b/MIPS.md
@@ -0,0 +1,8 @@
+:computer-architecture: :isa:
+# MIPS
+
+CA L3
+
+## Notes
+
+
diff --git a/MUX.md b/MUX.md
@@ -0,0 +1,8 @@
+:computer-architecture:
+# MUX
+
+CA L3
+
+## Notes
+
+**Definition:** A MUX is a multiplexer which allows multiple inputs and selects one to be the output. This is also known as a data selector.
diff --git a/MachineLearning.md b/MachineLearning.md
@@ -43,6 +43,7 @@ Concepts:
[[ClassificationProblem.md]]
[[SupportVectorMachine.md]]
[[ClusteringAlgorithms.md]]
+[[EigenVector.md]]
To do:
@@ -50,4 +51,3 @@ To do:
[[DeepLearning.md]]
[[Kernels.md]]
[[Backpropagation.md]]
-[[EigenVector.md]]
diff --git a/MathConceptsCS331.md b/MathConceptsCS331.md
@@ -0,0 +1,9 @@
+:cs331: :math:
+# Math Concepts CS 331
+
+Math Relating to CS331.
+
+## Notes
+
+[[DotProduct.md]]
+[[Determinant.md]]
diff --git a/MicroArchitecture.md b/MicroArchitecture.md
@@ -8,3 +8,9 @@ Computer Architecture L2
**Definition:** The implementation of an agreed upon ISA. These are the underlying mechanics that are not exposed to the OS/System developer.
There are many micro architecture implementations of each ISA, but very few different ISAs because changes to ISAs breaks compatibility.
+
+This is anything in hardware not exposed to software. This includes speculative execution (preloading data), [[SuperScalar.md]], and [[OutOfOrderExecution.md]].
+
+Most of the time [[Cache.md]] is not exposed to the programmer, but sometimes these things are.
+
+Microarchitecture can also set core frequency, but this is sometimes in the [[ISA.md]] which means it is not always.
diff --git a/Opcode.md b/Opcode.md
@@ -0,0 +1,10 @@
+:computer-architecture: :isa:
+# Opcode
+
+CA L3
+
+## Notes
+
+**Definition:** An opcode is the first part of an [[Instruction.md]] which describes what the instruction does.
+
+This is a form of [[BitSteering.md]]
diff --git a/Operands.md b/Operands.md
@@ -0,0 +1,10 @@
+:computer-architecture: :isa:
+# Operands
+
+CA L3
+
+## Notes
+
+**Definition:** Operands describe who an [[Instruction.md]] should be done to.
+
+See [[Opcode.md]] for the other part of an instruction.
diff --git a/PipelineControl.md b/PipelineControl.md
@@ -1 +1,8 @@
-:todo:
+:computer-architecture:
+# Pipline Control
+
+CA L3
+
+## Notes
+
+**Definition:** Pipline control describes the management and coordinatei
diff --git a/Pipelining.md b/Pipelining.md
@@ -0,0 +1,10 @@
+:computer-architecture:
+# Pipelining
+
+CA L3
+
+## Notes
+
+**Definition:** Pipelining is the use of CPU hardware such that simultaneous execution of more than one instruction occurs at the same time.
+
+See [[OutOfOrderExecution.md]]
diff --git a/ProgrammerVisibleState.md b/ProgrammerVisibleState.md
@@ -0,0 +1,16 @@
+:computer-architecture:
+# Programmer Visible State
+
+CA L3
+
+## Notes
+
+**Definition:** Programmer visible state is all state of program execution that is visible to programs.
+
+This includes the program counter, registers, and memory.
+
+This is all information visible to the programmer.
+
+See [[ISA.md]] for more related content.
+
+There is also programmer invisible state which includes cache and pipline registers are example of state in the [[MicroArchitecture.md]]
diff --git a/EigenVector.md b/RISC.md
diff --git a/EigenVector.md b/VLIW.md
diff --git a/VonNeumannModel.md b/VonNeumannModel.md
@@ -12,3 +12,11 @@ This is our broad model for computing and computer architecture. Additionally, t
Sequential instruction processing is ensured using a program counter that states what is being processed currently.
Alternatives listed in [[ForwardThoughts.md]]
+
+---
+
+Two key properties:
+
+Stored Program
+
+Sequential Instruction Processing
