commit 325457d2f05a2639c95e13dcb9741bc06e7f0912
parent 0d4946ca6d354f8b0f1ee3d57a5dc1e5b6b7ecff
Author: Andrew <andrewlaack1@gmail.com>
Date: Thu, 18 Apr 2024 05:59:35 -0500
Completed lecture 2
Diffstat:
22 files changed, 167 insertions(+), 11 deletions(-)
diff --git a/Algorithm.md b/Algorithm.md
@@ -0,0 +1,10 @@
+:cs331: :cs202: :computer-architecture:
+# Algorithm
+
+Computer Architecture L2
+
+## Notes
+
+**Definition: ** A step by step procedure to solve a problem where each step is definite (quantifiable), computable, and finite (ends eventually).
+
+This was described in computer architecture as despite algorithms being implemented in software, there are also algorithms involved in computer architecture.
diff --git a/BarrierSynchronization.md b/BarrierSynchronization.md
@@ -0,0 +1,18 @@
+# Barrier Synchronization
+
+Computer Architecture L2
+
+## Notes
+
+**Definition:** This is a way to block all execution until all inputs are ready. This can be thought of as thread syncing and is closely related to [[DataFlow.md]] execution.
+
+
+in1 in2 in3
+
+BLOCKERBLOCKER
+
+out1 out2 out3
+
+in this image, all in's need to be ready before out's are assigned.
+
+See [[BulkSynchronousProcessing.md]] for more of the same information. Bulk synchronous processing is the idea of processing lots of things in parallel before moving on.
diff --git a/BulkSynchronousProcessing.md b/BulkSynchronousProcessing.md
@@ -0,0 +1,11 @@
+# Bulk Synchronous Processing
+
+CA L2
+
+## Notes
+
+**Definition:** Completing parallel processing and then using [[BarrierSynchronization.md]] to join together threads of execution.
+
+This is called bulk because it can be done all concurrently while also having synchronization in the form of a thread join.
+
+Introduced by Leslie Valiant
diff --git a/CircuitTechnology.md b/CircuitTechnology.md
@@ -1,5 +1,5 @@
-:computer-architecture:
-#Circuit Technology
+:computer-architecture: :todo:
+# Circuit Technology
Discussion of materials, gates, and things of that sort.
diff --git a/ComputerArchitecture.md b/ComputerArchitecture.md
@@ -11,18 +11,27 @@ Links to information learned from computer architecture course
## Main Links
-[[CircuitTechnology.md]]
[[HistoricalDesigns.md]]
-[[ForwardThoughts.md]]
[[Abstraction.md]]
[[Memory.md]]
[[Scheduling.md]]
+[[Algorithm.md]]
+[[ISA.md]]
+[[OutOfOrderExecution.md]]
+[[SuperScalar.md]]
+[[MooresLaw.md]]
+[[ForwardThoughts.md]]
+[[DRAMRowHammer.md]]
+[[VonNeumannModel.md]]
+[[BarrierSynchronization.md]]
To do:
[[Hamming.md]]
+[[PipelineControl.md]]
+[[CircuitTechnology.md]]
[[SRAM.md]]
-[[ISA.md]]
[[MicroArchitecture.md]]
[[Cache.md]]
[[BloomFilter.md]]
+
diff --git a/DRAMRowHammer.md b/DRAMRowHammer.md
@@ -0,0 +1,7 @@
+# DRAM Row Hammer
+
+Computer Architecture L1
+
+## Notes
+
+See [[DisturbanceErrors.md]] for more information as it describes this vulnerability.
diff --git a/DataFlow.md b/DataFlow.md
@@ -0,0 +1,15 @@
+# Data Flow
+
+Computer Architecture L2
+
+## Notes
+
+**Definition:** This is a theory of computation that stipulates execution of code should be on a dependence basis instead of in order. If one instruction is dependent upon another that has not been executed it should not be executed, but if all dependencies have been executed then the code can be executed, if chosen to.
+
+This model is in contrast with [[VonNeumannModel.md]] where everything is sequential.
+
+Data flow can be easily visualized as a graph.
+
+This paradigm requires a differently designed processor.
+
+This paradigm is also, sort of, implemented via [[OutOfOrderExecution.md]]
diff --git a/DisturbanceErrors.md b/DisturbanceErrors.md
@@ -3,4 +3,6 @@
## Notes
+Also referred to as [[DRAMRowHammer.md]]
+
These are caused by frequent accesses of a given row. When a row is moved to the [[RowBuffer.md]] there is a (precharge) high charge applied to it and a low charge applied to the one being moved out of the buffer. This activation over and over to the same row can cause errors in adjacent rows because of how close together dram rows are. This increases the rate of charge leakage in adjacent rows. This issue has been resolved in flash by a controller that stores error correcting codes and checks over and over. There are still issues with this memory, but ecc resolves this issue when needed just more expensive.
diff --git a/ForwardThoughts.md b/ForwardThoughts.md
@@ -5,4 +5,20 @@ Things that could be possible and necessary for future development
## Notes
+There will need to be architecture capable of allowing higher levels of computation. We need to consider future scaling.
+In the future architecture may need to enable:
+
+1. Life like 3D visualization
+2. Virtual Reality
+3. Personalized Genomics/Medicine
+
+Solutions to [[DRAMRowHammer.md]].
+
+Alternatives to Von Neumann Model:
+
+1. Multi Processors
+ - Each processor is Von Neumann, but there is parallel processing which is not
+2. [[DataFlow.md]]
+3. [[BulkSynchronousProcessing.md]]
+ - This is the common way of doing synchronous processing while using Von Neumann constrained processors
diff --git a/GameObject.md b/GameObject.md
@@ -1,5 +1,5 @@
:unity: :cs331:
-#Game Object
+# Game Object
CS 331 W12 L3
diff --git a/ISA.md b/ISA.md
@@ -0,0 +1,11 @@
+:computer-architecture:
+# Instruction Set Architecture
+
+Computer Architecture L2
+
+## Notes
+
+**Definition:** The design of the interconnection between hardware and software to create a functional computing system.
+
+This is the agreed upon interface between os/vm/higher level things and lower level [[MicroArchitecture.md]]. This information is necessary to know for the OS developer.
+
diff --git a/Input.md b/Input.md
@@ -1,3 +1,4 @@
+:unity: :cs331: :movement:
# Input
CS 331 W12 L1
diff --git a/MicroArchitecture.md b/MicroArchitecture.md
@@ -0,0 +1,8 @@
+:computer-architecture:
+# Micro Architecture
+
+Computer Architecture L2
+
+## Notes
+
+**Definition:** The implementation of an agreed upon ISA. These are the underlying mechanics that are not exposed to the OS/System developer.
diff --git a/MooresLaw.md b/MooresLaw.md
@@ -0,0 +1,12 @@
+:computer-architecture:
+# Moore's Law
+
+Computer architecture L2.
+
+## Notes
+
+**Definition:**Component counts double every other year.
+
+This was found by examining a log base 2 function to find that the function was linear and as such the underlying function is exponential (x^2).
+
+He also found that the relative cost was decreasing, but the higher end was consistently expensive or increasingly so.
diff --git a/Movement.md b/Movement.md
@@ -12,16 +12,16 @@ A common way to move is by doing this:
```csharp
float speed = 2.0f; //assign default movement speed
-float rotationRate = 10.0f; //assign default rate of rotation
+float rotationRate = 30.0f; //assign default rate of rotation
bool moveForward = Input.GetKey("up");
if (moveForward){
- transform.position += transform.forward * speed * Time.deltaTime();
+ transform.position += transform.forward * speed * Time.deltaTime;
}
bool rotateLeft = Input.GetKey("left"); //this assumes rotation is done by keyboard input
if(rotateLeft){
- transform.Rotate(0, rotationRate * Time.deltaTime(), 0);
+ transform.Rotate(0, -rotationRate * Time.deltaTime, 0);
}
```
The issue with this is movement may not feel natural because there is no acceleration being applied to the object you are just moving it by a certain amount. In essence, you are assigning a velocity to the object for the frames where the "up" key is pressed.
diff --git a/OutOfOrderExecution.md b/OutOfOrderExecution.md
@@ -0,0 +1,10 @@
+:computer-architecture: :optimization:
+# Out of Order Execution
+
+Computer Architecture L2
+
+## Notes
+
+**Definition:** An optimization strategy that executes commands out of order to reduce the amount of clocks/time taken to complete computations. This is complex as it can be hard to determine if a command relies upon another command that came in earlier.
+
+See [[DataFlow.md]] for more information about out of order/non-Von Neumann computation.
diff --git a/Quaternions.md b/Quaternions.md
@@ -1,5 +1,4 @@
:cs331: :unity:
-
# Quaternions
CS 331 W11 L2
diff --git a/SuperScalar.md b/SuperScalar.md
@@ -0,0 +1,8 @@
+:computer-architecture:
+# Super Scalar
+
+Computer Architecture L2
+
+## Notes
+
+**Definition:** Execute multiple instructions per cycle.
diff --git a/Triangulation.md b/Triangulation.md
@@ -1,5 +1,4 @@
:cs331: :unity:
-
# Triangulation
CS 331 W11 L2
diff --git a/VonNeumannModel.md b/VonNeumannModel.md
@@ -0,0 +1,14 @@
+:computer-architecture:
+# Von Neumann Model
+
+Computer Architecture L2
+
+## Notes
+
+**Definition:** Control signals are used to create a distinction between data and instructions in memory, but they are both saved together. Additionally, instructions are completed sequentially ie. finish one, fetch the next compute, etc.
+
+This is our broad model for computing and computer architecture. Additionally, there is a single bus for memory (I would think having more could cause concurrency issues), a program control unit (control signals), and an arithmetic unit (cpu).
+
+Sequential instruction processing is ensured using a program counter that states what is being processed currently.
+
+Alternatives listed in [[ForwardThoughts.md]]
diff --git a/index.md b/index.md
@@ -14,3 +14,8 @@ This is the index for my main note classifications. I will maintain this as a ho
[[ComputerArchitecture.md]]
[[LinuxStuff.md]]
+
+## Technology Books to Read
+
+- [ ] "The Structure of Scientific Revolutions" - Thomas Kuhn
+- [ ] "Introduction to Computing Systems" - Patt and Patel
diff --git a/rsync.md b/rsync.md
@@ -1,3 +1,4 @@
+:linux: :self-hosting:
# Rsync
Notes on backups with rsync
