commit 2470e9388c1c5bab6e7fb35ec34c943fca217038
parent ff31dd9e2efe0316c4cdd3478c550501407a7a8b
Author: Andrew <andrewlaack1@gmail.com>
Date: Tue, 16 Apr 2024 07:38:54 -0500
Completed first computer architecture lecture
Diffstat:
22 files changed, 169 insertions(+), 4 deletions(-)
diff --git a/Abstraction.md b/Abstraction.md
@@ -0,0 +1,10 @@
+:cpu-architecture: :oop:
+# Abstraction
+
+Abstraction cpu architecture L1
+
+## Notes
+
+Abstraction hides away the implementation details to higher levels. You only see the interfaces provided to you.
+
+There are instances where exposing lower level functions to higher can be useful. This can be seen when lower level instructions are shown to the compiler to allow better optimization.
diff --git a/CS331.md b/CS331.md
@@ -3,6 +3,6 @@
This is the index for my CS 332 notes.
-# Main Links
+## Main Links
[[Unity]]
diff --git a/Cache.md b/Cache.md
@@ -0,0 +1,6 @@
+:computer-architecture: :cpu: :cache:
+# Cache
+
+## Notes
+
+
diff --git a/CircuitTechnology.md b/CircuitTechnology.md
@@ -0,0 +1,8 @@
+:computer-architecture:
+#Circuit Technology
+
+Discussion of materials, gates, and things of that sort.
+
+## Notes
+
+
diff --git a/ComputerArchitecture.md b/ComputerArchitecture.md
@@ -0,0 +1,28 @@
+:computer-architecture: :index:
+# Computer Architecture
+
+Links to information learned from computer architecture course
+
+## Questions I would like to answer
+
+1. Generally, how does a CPU work and how does it interface with other computer components?
+2. Why do ARM chips with a reduced instruction set appear to be more efficient?
+3. What are the steps to create a computer in a video game?
+
+## Main Links
+
+[[CircuitTechnology.md]]
+[[HistoricalDesigns.md]]
+[[ForwardThoughts.md]]
+[[Abstraction.md]]
+[[Memory.md]]
+[[Scheduling.md]]
+
+To do:
+
+[[Hamming.md]]
+[[SRAM.md]]
+[[ISA.md]]
+[[MicroArchitecture.md]]
+[[Cache.md]]
+[[BloomFilter.md]]
diff --git a/DRAM.md b/DRAM.md
@@ -0,0 +1,13 @@
+:computer-architecture: :memory:
+# DRAM
+
+DRAM is what we think of as RAM. See [[Memory.md]] for other links.
+
+## Notes
+
+
+[[DRAMBanks.md]] are a 2d matrix of [[DRAMCell.md]] and it is accessed by rows. When the processor wants a row, it activates the row, sends it to the [[RowBuffer.md]], and then sends the data out. Subsequent accesses of a different column are very fast because the row is already in a buffer. This can be thought of cached rows.
+
+One optimization done is to prioritize memory requests associated with memory that is already buffered to decrease context switching. This causes issues with multiple applications because it will prioritize applications that use localized memory more often. You can also create programs that take advantage of this to deny memory from other applications. On the flip side, if you are simply using an oldest request scheduling algorithm then random access requests will take more time and thus if one application uses more of them it will get more time than the other application.
+
+[[DRAMChips.md]] are the larger DRAM unit that includes both the Banks and associated circuitry.
diff --git a/DRAMBanks.md b/DRAMBanks.md
@@ -0,0 +1,6 @@
+:memory: :computer-architecture:
+# DRAM Banks
+
+## Notes
+
+**Definition:** 2d bank of [[DRAMCell.md]] that is accessed by a row at a time rows may be around 8kb in size.
diff --git a/DRAMCell.md b/DRAMCell.md
@@ -0,0 +1,8 @@
+:memory: :computer-architecture:
+# DRAM Cell
+
+## Notes
+
+A DRAM Cell is the cell used to store one bit of information. It is made of a capacitor and an access transistor. The data is stored in the charge of the capacitor.
+
+The access transistor is how you are able to query them. Since the access transistor is not perfect nor is the transistor they leak energy over time. As such they need to be refreshed over time using [[DRAMRefresh.md]].
diff --git a/DRAMChips.md b/DRAMChips.md
@@ -0,0 +1,6 @@
+:memory: :computer-architecture:
+# DRAM Chips
+
+## Notes
+
+DRAM Chips are the chips that contain the [[DRAMBanks.md]] along with associated circuitry. There are many chips (I think normally 8) that make up a RAM module.
diff --git a/DRAMRefresh.md b/DRAMRefresh.md
@@ -0,0 +1,12 @@
+:memory: :cpu-architecture:
+# DRAM Refresh
+
+## Notes
+
+This is the process of refreshing the energy stored in a [[DRAMCell.md]]'s capacitor so that losses in energy over time do not cause loss of data (bitrot).
+
+Currently, as of 2015, refreshes are required every 64ms. This costs electricity, can cause blocking issues, and as there is scaling these computations become slower and more power consuming. As an example, with 64gb DRAM refreshes can take up to 46% of time while 4gb is about 8%
+
+There is little coordination between the OS and the memory controller and the memory controller can't store information about what memory is allocated. This means that instead of just refreshing allocated memory, all memory is refreshed at the given frequency.
+
+This process is ran every 64ms and while most [[DRAMCell.md]]'s can go much longer than 64ms the LCD is 64ms. This is a bar for manufacturing that causes bad RAM to be thrown away. The memory controller could probably be smarter about this, but this is not done. These thoughts about how to optimize these things are RAIDR which is Retention aware intelligent DRAM refresh particularly thing thinking about [[BloomFilter.md]] usage to track which cells need more frequent refreshes. This can reduce refreshes by 74.6% at the cost of 1.25kb of memory with 8gb chips.
diff --git a/DisturbanceErrors.md b/DisturbanceErrors.md
@@ -0,0 +1,6 @@
+:memory: :computer-architecture: :flash-memory:
+# Disturbance Errors
+
+## Notes
+
+These are caused by frequent accesses of a given row. When a row is moved to the [[RowBuffer.md]] there is a (precharge) high charge applied to it and a low charge applied to the one being moved out of the buffer. This activation over and over to the same row can cause errors in adjacent rows because of how close together dram rows are. This increases the rate of charge leakage in adjacent rows. This issue has been resolved in flash by a controller that stores error correcting codes and checks over and over. There are still issues with this memory, but ecc resolves this issue when needed just more expensive.
diff --git a/ForwardThoughts.md b/ForwardThoughts.md
@@ -0,0 +1,8 @@
+:computer-architecture:
+# Forward Thoughts
+
+Things that could be possible and necessary for future development
+
+## Notes
+
+
diff --git a/GameObject.md b/GameObject.md
@@ -1,3 +1,4 @@
+:unity: :cs331:
#Game Object
CS 331 W12 L3
diff --git a/Hamming.md b/Hamming.md
@@ -0,0 +1,12 @@
+:cpu-architecture:
+# Hamming
+
+He was a person who was influential to computing
+
+## Notes
+
+**Hamming Distance:** The difference between two strings. This is defined as the number of positions that are different.
+
+Hamming distance led to the inception of error correction (hamming codes)
+
+**Hamming Codes:** :todo:
diff --git a/HistoricalDesigns.md b/HistoricalDesigns.md
@@ -0,0 +1,8 @@
+:computer-architecture:
+# Historical Designs
+
+Discussion of designs used historically and things we can take away.
+
+## Notes
+
+There is a trade off taken historically to use many cores instead of a single powerful core. It is much easier to architect simple cores that chain together than to architect one powerful core. This has a trade off in that it requires developers higher in the stack to ensure their code takes advantage of all of the cores using parallelization.
diff --git a/ISA.md b/ISA.md
diff --git a/Math310.md b/Math310.md
@@ -3,7 +3,7 @@
This is the index for my main Math 310 notes.
-# Main Links
+## Main Links
[[Induction.md]]
diff --git a/Memory.md b/Memory.md
@@ -0,0 +1,18 @@
+:memory: :computer-architecture:
+# Memory
+
+Memory information from computer architecture course
+
+## Notes
+
+Memory performance can affect compute speed of multiple applications running concurrently. This results in poorer performance for one despite having the clocks needed to computer correctly (denial of memory). Using nice does not change this which is the priority system for OSes. This is being caused by the DRAM memory controller being shared and thus causing a bottleneck.
+
+## Links
+
+[[DRAM.md]]
+[[DRAMChips.md]]
+[[DRAMCell.md]]
+[[RowBuffer.md]]
+[[DRAMBanks.md]]
+[[DRAMRefresh.md]]
+[[DisturbanceErrors.md]]
diff --git a/MicroArchitecture.md b/MicroArchitecture.md
diff --git a/RowBuffer.md b/RowBuffer.md
@@ -0,0 +1,10 @@
+:memory: :computer-architecture:
+# Row Buffer
+
+## Notes
+
+**Definition:** The row buffer is the buffer used to cache a row that is from [[DRAM.md]]. This is used because it is 2-3 times more efficient to query a buffered memory address than it is to query for a new row in memory. This is handled by the DRAM memory controller.
+
+Precharging is where the memory controller replaces the current buffered row with a new one that was requested this is done by sending highvoltage to the new and low voltage to the old. When these conflicts occur, this is 2-3 times slower than if the row was already cached.
+
+An example of a row size (and buffer size) is 8kb. This is just an example to illustrate a point.
diff --git a/Scheduling.md b/Scheduling.md
@@ -0,0 +1,6 @@
+:computer-architecture: :cpu: :os:
+# Scheduling
+
+## Notes
+
+CPU Scheduling is done on the OS level and is generally simply about the clocks given. This can cause issues with [[DRAM.md]] because the DRAM controller prioritizes requests associated with buffered rows of memory meaning that even if two processes have the same priority they will not necessarily get the same access to memory because of optimizations done in the DRAM controller.
diff --git a/index.md b/index.md
@@ -12,6 +12,5 @@ This is the index for my main note classifications. I will maintain this as a ho
## Other
-N/A
-
+[[ComputerArchitecture.md]]
