ISA.md (2294B)
1 # Instruction Set Architecture 2 3 Computer Architecture L(2,3) 4 5 **Definition:** The design of the interconnection between hardware and software to create a functional computing system. 6 7 This is the agreed upon interface between os/vm/higher level things and lower level [MicroArchitecture](MicroArchitecture.md) This information is necessary to know for the OS developer. 8 9 The ISA also includes register things and sometimes the CPU frequency/voltage. 10 11 [Pipelining](Pipelining.md) is generally not part of the ISA on newer systems. 12 13 Some ISAs have additional room for un-implemented instructions that would allow for future expansion. 14 15 --- 16 17 0-address machines (stack machines) are machines that only take [Opcode](Opcode.md) but not [[Operands.md]]. 0-address takes up less space in code, everything is already on the stack, but it can be very slow and can't express all computations easily (consider order of operations). 18 19 2-address machines are source + destination for operands. This does not preserve the value of the destination which requires copying overhead. x86 is 2-address. 20 21 3-address machines are source 1, source 2, and destination. Alpha is 3-address as is MIPS and ARM. 22 23 --- 24 25 The ISA also defines the supported datatypes. Some common ones include int, float, character. Sometimes they can include linked lists, stacks, queues, and strings. 26 27 With more/high level datatypes in the ISA we have smaller code, more cpu complexity, but simpler compilers. This basically means harder for [MicroArchitecture](MicroArchitecture.md) development, but easier for compiler developer. 28 29 This ties into semantic gap which describes the difference between the ISA and what programmers are trying to do with respect to datatypes and opcodes. When there are more datatypes, the semantic gap is low. The inverse is also true. 30 31 Virtual memory support is also part of the ISA. 32 33 --- 34 35 There is also another division in ISAs being load/store vs memory/memory architecture. 36 37 Load/store allows instructions to only run on registers. These are most RISC ISAs including MIPS and ARM. 38 39 Memory/memory can operate on memory locations as well as registers. These are most CISC ISAs including x86. 40 41 --- 42 43 Orthogonal ISA 44 45 Orthogonal ISAs allow for all opcodes to be used regardless of addressing mode. 46 47 --- 48