Cache.md (617B)
1 # Cache 2 3 **Source:** CS 6200 4 5 **Chapter:** P2L1 6 7 **Definition:** The processor cache is often implemented on SRAM and dramatically decreases memory read costs, going from hundreds of cycles for direct memory access to a few cycles when the data is cached. 8 9 ## Specifics 10 11 - Hot and cold cache 12 - The cache is hot when the cache is populated by the current process's memory 13 - The cache is cold when the current process's memory is not loaded into the cache, resulting in cache misses 14 - L1, L2, and L3 15 - Each level is often larger, but slower than the prior 16 17 See also [context switching](ContextSwitching.md)